FPGA Design Engineers
4 needed at senior or intermediate levels – all are full-time, permanent positions. Cherry Hill / Camden / Philadelphia area. Our client delivers high-quality secure communications systems. Relocation is provided if needed. US citizenship is required; active secret clearance is preferred.
• Responsible for architecture, implementation, verification /validation through software integration test for delivery of complex FPGAs AND/OR ASICs systems.
• develop architectures for implementation of high throughput complex designs involving Cryptographic Algorithms (VHDL, HLS) with
• work with high speed protocols– NVMe, PCIe/SRIOV, 10G-400G Ethernet, TCP/IP, and IP
• Development and integration of ARM SOC FPGAs (Ex. Xilinx MPSOC) AND/OR ASICs.
• writing/debugging tests/sequences for End-to-End simulation on UVM framework
• work with System Verilog Assertions
• Write and debug C++ based SW driven validation on SOC evaluation boards (Xilinx MPSOC) running Linux.
• Utilize EDA flows and methodologies including Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA including HLS, Mentor Questa family, VIPs for UVM, Clock Domain Crossing (CDC), Catapult (HLS).
• At least 5 year experience with proven track record of implementing complex algorithms in networking ASIC/FPGAs
• BS in EE or CS; MS preferred
• Proficiency in VHDL, C++ (OOP), system Verilog Assertions (SVA), ARM, Linux OS, high speed protocols (TCP/IP, Ethernet, etc.), analytical and debugging skills
• Good verbal, written, and presentation skills
• US Government Secret security clearance or ability to obtain clearance required
• US Citizenship required
A PLUS for prior experience with:
• High Level Synthesis (HLS) with Vivado, Mentor Catapult
• Xilinx MPSOC, and Vivado SDK and Linux super user
• Cryptographic and high speed networking designs